Among the analog-to-digital converters (ADCs), successive approximation register analog-to-digital converters (SAR ADCs) are the commonly used ADCs. The conversion process of the SRA ADCs is analogous to measuring weight by a balance. The SAR ADC compares the input analog signal with the different reference voltages for a few times to cause the obtained digital value to successively approach the input analog value. The reference voltages are often generated by a digital-to-analog convertor (DAC). The SAR ADCs include synchronous successive approximation register analog-to-digital converters (SSAR ADCs) and asynchronous successive approximation register analog-to-digital converters (ASAR ADCs). The SSAR ADC compares the input analog signal with the reference voltage one time in one period. Comparing with the SSAR ADCs, the ASAR ADCs have a different control logic. The ASAR ADCs are able to finish all comparisons between the input analog signal and the reference voltages in one period. Thus, the ASAR ADCs have a higher conversion speed.
FIG. 1 illustrates a circuit diagram of an existing ASAR ADC 10. The ASAR ADC 10 includes a sample/hold circuit 101, a comparison circuit 103, an Exclusive-OR gate circuit 104, an ASAR logic circuit 105 and a DAC circuit 102. The input signal “Vin” is connected to the first input terminal of the comparison circuit 103 through the sample/hold circuit 101. The output voltage “Vcomp” of the comparison circuit 103 is connected to the Exclusive-OR gate circuit 104 and the ASAR logic circuit 105. The output terminal of the Exclusive-OR gate circuit 104 is connected to the ASAR logic circuit 105. The ASAR logic circuit 105 performs a logic calculation according to the input signal “Vin”; and the digital output signal “Vout” is obtained as an output signal. The output signal is used as a control signal; and is transferred into the input terminal of the DAC circuit 102. The output signal of the DAC circuit 102 is transmitted to the second input terminal of the comparison circuit 103. The comparison circuit 103 responds to the “Latch” signal, and compares the input signals. When the comparison is finished, the “Flag” signal outputted by the Exclusive-OR gate circuit 104 becomes a valid signal; and is identified by the ASAR logic circuit 105. The ASAR logic circuit 105 controls the comparison circuit 103 to start a next comparison process.
However, the comparison circuit of the existing ASAR ADC has a metastable issue. The metastable issue affects the performance of the ASAR ADCs, including the effective digits, etc. Accordingly, the applications of the ASAR ADCs are limited. The disclosed circuit structures and methods are directed to solve one or more problems set forth above and other problems in the art.